# Neoarcheon computer

<sub>*Neoarcheon means "The new dawn of ancient times".
It comes from "[Neo](https://en.wiktionary.org/wiki/neo-)", a prefix for "New", and "[Eoarchean](https://en.wikipedia.org/wiki/Eoarchean)", the era in which life began.*</sub>

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## Summary

1. [Aims and challenges](#aims-and-challenges)
2. [Design](#design)
    1. [Core architecture](#core-architecture)
    2. [Registers and memory map](#registers-and-memory-map)
    3. [The instruction set](#the-instruction-set)

## Aims and challenges

Make a turing complete computer from scratch.

At first every part of the computer will be the "industrial" version :
 - The CPU from logic gates.
 - The RAM a [SRAM](https://en.wikipedia.org/wiki/Static_random-access_memory) chip (*[UM61256BK-20](/Documents/Datasheets/UM61256.pdf) from 1993*)
 - The ROM another chip (*[D27C010](/Documents/Datasheets/D27C010-200V10.pdf) from 1986 !*)

Then the aim is to replace them with made from scratch versions.
For the moment only the RAM is meant to be replaced with homemade [magnetic core RAM](https://en.wikipedia.org/wiki/Magnetic-core_memory).

**NOT ANY SORTS OF AI WILL BE USED IN THIS PROJECT.**

*Why ?*

People in the 70s got someone on the moon with their brain, and made him come back.
AI is useful for medicine, protein research or other deep research subjects.
I do not need a LLM to understand and make a computer.

## Design

The design is inspired of great people hard work :
 - [Ben Eater's 8 bits breadboard computer](https://eater.net/8bit)
 - [Mattbatwings's Minecraft computer tutorial](https://youtu.be/hAZEXqWLTmY?si=qgic0b28PMeOPs_l)

The core architecture is inspired of the legendary [Intel's MCS-51](/Documents/Datasheets/8051.PDF) [microcontroller series](https://en.wikipedia.org/wiki/Intel_MCS-51).

The computer is in 8 bits. The target frequency of the processor is 10mHz

### Core architecture

![Computer diagram.](/Documents/Computer%20diagram.svg)
<sub>Made with [Drawio](https://www.drawio.com/).</sub>

### Registers and memory map

| Name | Long Name               | Description                  |
| :--: | :---------------------- | :--------------------------- |
|  IR  | Instruction Register    | Running instruction storage. |
|  A   | A Register              | ALU first input register.    |
|  B   | B Register              | ALU second input register.   |
|  PSW | Program Status Word     | Status flags.                |
|  MAR | Memory Address Register | RAM heap access address.     |
|  SP  | Stack pointer           | RAM stack access pointer.    |

###### PSW Structure

| Bit | Name | Long Name | Description                                 |
| :-: | :--: | :-------- | :------------------------------------------ |
|  0  |  Z   | Zero      | Is true if the ALU result is equal to zero. |
|  1  |  C   | Carry     | Is true if an ALU calculation overflows.    |
|  2  |      |           |                                             |
|  3  |      |           |                                             |
|  4  |      |           |                                             |
|  5  |      |           |                                             |
|  6  |      |           |                                             |
|  7  |      |           |                                             |

### The instruction set

Every instruction is 1 to 3 bytes long.
First is the opcode, and the optionnal 2 bytes are the operands.
Operands can be an data (1B), address (1B), or full address (2B).

These are only real instructions. Pseudoinstruction will be defined later.

| Mnemonic  | Description   | Pseudocode    |
| :-------: | :------------ | :------------ |
| 
