From 5b4ed329cc9e15806bd2ec2a43aa21558d91891e Mon Sep 17 00:00:00 2001
From: Ulysse Cura <ulysse.cura@gmail.com>
Date: Sat, 11 Jul 2026 09:10:38 +0200
Subject: [PATCH] Starting instruction set and memory map.

---
 README.md | 47 ++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 40 insertions(+), 7 deletions(-)

diff --git a/README.md b/README.md
index 04c1808..e9bde14 100644
--- a/README.md
+++ b/README.md
@@ -12,7 +12,9 @@ It comes from "[Neo](https://en.wiktionary.org/wiki/neo-)", a prefix for "New",
 1. [Aims and challenges](#aims-and-challenges)
 2. [Design](#design)
     1. [Core architecture](#core-architecture)
-    2. [Registers and memory map](#registers-and-memory-map)
+        1. [ALU functions](#alu-functions)
+        2. [Registers](#registers-and-memory-map)
+        3. [Memory map](#memory-map)
     3. [The instruction set](#the-instruction-set)
 
 ## Aims and challenges
@@ -43,22 +45,47 @@ The design is inspired of great people hard work :
 
 The core architecture is inspired of the legendary [Intel's MCS-51](/Documents/Datasheets/8051.PDF) [microcontroller series](https://en.wikipedia.org/wiki/Intel_MCS-51).
 
-The computer is in 8 bits. The target frequency of the processor is 10mHz
+The computer is in 8 bits. The target frequency of the processor is 10mHz.
 
 ### Core architecture
 
 ![Computer diagram.](/Documents/Computer%20diagram.svg)
 <sub>Made with [Drawio](https://www.drawio.com/).</sub>
 
-### Registers and memory map
+#### ALU functions
+
+###### Logic Functions
+
+|  Func  | Description    |
+| :----: | :------------- |
+|   !A   | Not A.         |
+|   !B   | Not B.         |
+|   A+B  | A or B.        |
+|   AB   | A and B.       |
+|   A^B  | A xor B.       |
+| !(A+B) | Not (A or B).  |
+| !(AB)  | Not (A and B). |
+| !(A^B) | Not (A xor B). |
+
+###### Arithmetic Functions
+
+|  Func  | Description |
+| :----: | :---------- :
+|  A+1   |
+|  A-1   |
+|  A+B   |
+|  A-B   |
+
+#### Registers
 
 | Name | Long Name               | Description                  |
 | :--: | :---------------------- | :--------------------------- |
 |  IR  | Instruction Register    | Running instruction storage. |
-|  A   | A Register              | ALU first input register.    |
-|  B   | B Register              | ALU second input register.   |
-|  PSW | Program Status Word     | Status flags.                |
-|  MAR | Memory Address Register | RAM heap access address.     |
+| Acc  | Accumulator Register    | ALU output register.         |
+| TMP1 | Temp 1 Register         | ALU first input register.    |
+| TMP2 | Temp 2 Register         | ALU second input register.   |
+| PSW  | Program Status Word     | Status flags.                |
+| MAR  | Memory Address Register | RAM heap access address.     |
 |  SP  | Stack pointer           | RAM stack access pointer.    |
 
 ###### PSW Structure
@@ -74,6 +101,12 @@ The computer is in 8 bits. The target frequency of the processor is 10mHz
 |  6  |      |           |                                             |
 |  7  |      |           |                                             |
 
+#### Memory map
+
+| Address | Mapping |
+| :-----: | :------ |
+|  0x00   | 
+
 ### The instruction set
 
 Every instruction is 1 to 3 bytes long.