From 8182769e7966b7fc11f2ce0ff578c63269c72eba Mon Sep 17 00:00:00 2001
From: Ulysse Cura <ulysse.cura@gmail.com>
Date: Mon, 6 Jul 2026 15:13:38 +0200
Subject: [PATCH] Starting to add PSW Register.

---
 README.md | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/README.md b/README.md
index d95106e..efb64db 100644
--- a/README.md
+++ b/README.md
@@ -60,9 +60,16 @@ The CPU will have ports for inputs / outputs, not a north and south bridge.
 |  IR  | Instruction Register    | Running instruction storage. |
 |  A   | A Register              | ALU first input register.    |
 |  B   | B Register              | ALU second input register.   |
+|  PSW | Program Status Word     | Status flags.                |
 |  MAR | Memory Address Register | RAM heap access address.     |
 |  SP  | Stack pointer           | RAM stack access pointer.    |
 
+###### PSW Structure
+
+| Bit | Name | Description |
+| :-: | :--: | :---------- |
+|  0  | 
+
 ### The instruction set.
 
 Every instruction is 1 to 3 bytes long.