diff --git a/README.md b/README.md index efb64db..19de293 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,7 @@ # Neoarcheon computer -*Neoarcheon means "The new dawn of ancient times". It comes from "[Neo](https://en.wiktionary.org/wiki/neo-)", a prefix for "New" and "[Eoarchean](https://en.wikipedia.org/wiki/Eoarchean)", the first era in which life begun.* +*Neoarcheon means "The new dawn of ancient times". +It comes from "[Neo](https://en.wiktionary.org/wiki/neo-)", a prefix for "New", and "[Eoarchean](https://en.wikipedia.org/wiki/Eoarchean)", the era in which life began.* ---------- @@ -16,18 +17,13 @@ Make a turing complete computer from scratch. -The computer will be composed of : - - A CPU - - Some RAM - - Some ROM - -At first every part will be the "industrial" version : +At first every part of the computer will be the "industrial" version : - The CPU from logic gates. - The RAM a [SRAM](https://en.wikipedia.org/wiki/Static_random-access_memory) chip (*[UM61256BK-20](/Documents/Datasheets/UM61256.pdf) from 1993*) - The ROM another chip (*[D27C010](/Documents/Datasheets/D27C010-200V10.pdf) from 1986 !*) Then the aim is to replace them with made from scratch versions. -For the moment only the RAM is meant to be replaced with homemade magnetic core RAM. +For the moment only the RAM is meant to be replaced with homemade [magnetic core RAM](https://en.wikipedia.org/wiki/Magnetic-core_memory). **NOT ANY SORTS OF AI WILL BE USED IN THIS PROJECT.** @@ -41,19 +37,18 @@ I do not need a LLM to understand and make a computer. The design is inspired of great people hard work : - [Ben Eater's 8 bits breadboard computer](https://eater.net/8bit) - - [Mattbatwings's minecraft computer tutorial](https://youtu.be/hAZEXqWLTmY?si=qgic0b28PMeOPs_l) + - [Mattbatwings's Minecraft computer tutorial](https://youtu.be/hAZEXqWLTmY?si=qgic0b28PMeOPs_l) -The core architecture will be inspired of the legendary [Intel's MCS-51](/Documents/Datasheets/8051.PDF) [microcontroller series](https://en.wikipedia.org/wiki/Intel_MCS-51). +The core architecture is inspired of the legendary [Intel's MCS-51](/Documents/Datasheets/8051.PDF) [microcontroller series](https://en.wikipedia.org/wiki/Intel_MCS-51). -The computer will be in 8 bits. The target frequency of the processor is 10mHz -The CPU will have ports for inputs / outputs, not a north and south bridge. +The computer is in 8 bits. The target frequency of the processor is 10mHz ### Core architecture ![Computer diagram.](/Documents/Computer%20diagram.svg) Made with [Drawio](https://www.drawio.com/). -### Registers and memory map. +### Registers and memory map | Name | Long Name | Description | | :--: | :---------------------- | :--------------------------- | @@ -70,7 +65,7 @@ The CPU will have ports for inputs / outputs, not a north and south bridge. | :-: | :--: | :---------- | | 0 | -### The instruction set. +### The instruction set Every instruction is 1 to 3 bytes long. First is the opcode, and the optionnal 2 bytes are the operands. @@ -80,4 +75,4 @@ These are only real instructions. Pseudoinstruction will be defined later. | Mnemonic | Description | Pseudocode | | :-------: | :------------ | :------------ | -| \ No newline at end of file +|