diff --git a/Documents/Computer diagram.svg b/Documents/Computer diagram.svg new file mode 100644 index 0000000..553b3b5 --- /dev/null +++ b/Documents/Computer diagram.svg @@ -0,0 +1,4 @@ + + + +
ALU
RAM
RAM Addr.
Register
Stack
Pointer
Data Bus
8 bits
EPROM
Instruction
Register
Timing
and
Control
A
Register
B
Register
Buffer
 
 \ No newline at end of file diff --git a/Documents/Datasheets/8051.pdf b/Documents/Datasheets/8051.pdf new file mode 100644 index 0000000..e93a0cc Binary files /dev/null and b/Documents/Datasheets/8051.pdf differ diff --git a/Documents/D27C010-200V10.pdf b/Documents/Datasheets/D27C010-200V10.pdf similarity index 100% rename from Documents/D27C010-200V10.pdf rename to Documents/Datasheets/D27C010-200V10.pdf diff --git a/Documents/UM61256.pdf b/Documents/Datasheets/UM61256.pdf similarity index 100% rename from Documents/UM61256.pdf rename to Documents/Datasheets/UM61256.pdf diff --git a/README.md b/README.md index f842bae..c6399df 100644 --- a/README.md +++ b/README.md @@ -20,8 +20,8 @@ The computer will be composed of : At first every part will be the "industrial" version : - The CPU from logic gates. - - The RAM a [SRAM](https://en.wikipedia.org/wiki/Static_random-access_memory) chip (*[UM61256BK-20](/Documents/UM61256.pdf) from 1993*) - - The ROM another chip (*[D27C010](/Documents/D27C010-200V10.pdf) from 1986 !*) + - The RAM a [SRAM](https://en.wikipedia.org/wiki/Static_random-access_memory) chip (*[UM61256BK-20](/Documents/Datasheets/UM61256.pdf) from 1993*) + - The ROM another chip (*[D27C010](/Documents/Datasheets/D27C010-200V10.pdf) from 1986 !*) Then the aim is to replace them with made from scratch versions. For the moment only the RAM is meant to be replaced with homemade magnetic core RAM. @@ -37,7 +37,7 @@ I do not need a LLM to understand and make a computer. ## Architecture choices The computer will be in 8 bits since the RAM and ROM are meant to be in 8 bits. -The CPU will have ports for inputs / outputs. +The CPU will have ports for inputs / outputs, not a north and south bridge. ## Design @@ -45,13 +45,31 @@ The design is inspired of great people hard work : - [Ben Eater's 8 bits breadboard computer](https://eater.net/8bit) - [Mattbatwings's minecraft computer tutorial](https://youtu.be/hAZEXqWLTmY?si=qgic0b28PMeOPs_l) +The core architecture will be inspired of the legendary [Intel's MCS-51](/Documents/Datasheets/8051.PDF) [microcontroller series](https://en.wikipedia.org/wiki/Intel_MCS-51). + +### Core architecture + +![Computer diagram.](/Documents/Computer%20diagram.svg) +Made with [Drawio](https://app.diagrams.net/). + +### Registers + +| Name | Long Name | Description | +| :--: | :---------------------- | :--------------------------- | +| IR | Instruction Register | Running instruction storage. | +| A | A Register | ALU first input register. | +| B | B Register | ALU second input register. | +| MAR | Memory Address Register | RAM heap access address. | +| SP | Stack pointer | RAM stack access pointer. | + ### The instruction set. -Every instruction is 8 bits long. And there is 3 bytes of data after the instruction. -Because the ROM is 8 bits, every instruction will take 4 bytes. -This property might help for [instruction pipelining](https://en.wikipedia.org/wiki/Instruction_pipelining) in the future. +Every instruction is 1 to 3 bytes long. +First is the opcode, and the optionnal 2 bytes are the operands. +Operands can be an data (1B), address (1B), or full address (2B). These are only real instructions. Pseudoinstruction will be defined later. | Mnemonic | Description | Pseudocode | | :-------: | :------------ | :------------ | +| \ No newline at end of file diff --git a/Schematic/.history b/Schematic/.history new file mode 160000 index 0000000..2dc7cfb --- /dev/null +++ b/Schematic/.history @@ -0,0 +1 @@ +Subproject commit 2dc7cfbde8efcd6289bdb70eea196c68d6c2beee diff --git a/Schematic/Schematic.kicad_pcb b/Schematic/Schematic.kicad_pcb new file mode 100644 index 0000000..ccd82d6 --- /dev/null +++ b/Schematic/Schematic.kicad_pcb @@ -0,0 +1,2 @@ +(kicad_pcb (version 20260206) (generator "pcbnew") (generator_version "10.0") +) \ No newline at end of file diff --git a/Schematic/Schematic.kicad_prl b/Schematic/Schematic.kicad_prl new file mode 100644 index 0000000..c7537e1 --- /dev/null +++ b/Schematic/Schematic.kicad_prl @@ -0,0 +1,105 @@ +{ + "board": { + "active_layer": 0, + "active_layer_preset": "", + "auto_track_width": true, + "hidden_netclasses": [], + "hidden_nets": [], + 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