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Documents/Computer diagram.svg
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README.md
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@ -12,9 +12,7 @@ It comes from "[Neo](https://en.wiktionary.org/wiki/neo-)", a prefix for "New",
1. [Aims and challenges](#aims-and-challenges) 1. [Aims and challenges](#aims-and-challenges)
2. [Design](#design) 2. [Design](#design)
1. [Core architecture](#core-architecture) 1. [Core architecture](#core-architecture)
1. [ALU functions](#alu-functions) 2. [Registers and memory map](#registers-and-memory-map)
2. [Registers](#registers-and-memory-map)
3. [Memory map](#memory-map)
3. [The instruction set](#the-instruction-set) 3. [The instruction set](#the-instruction-set)
## Aims and challenges ## Aims and challenges
@ -45,47 +43,22 @@ The design is inspired of great people hard work :
The core architecture is inspired of the legendary [Intel's MCS-51](/Documents/Datasheets/8051.PDF) [microcontroller series](https://en.wikipedia.org/wiki/Intel_MCS-51). The core architecture is inspired of the legendary [Intel's MCS-51](/Documents/Datasheets/8051.PDF) [microcontroller series](https://en.wikipedia.org/wiki/Intel_MCS-51).
The computer is in 8 bits. The target frequency of the processor is 10mHz. The computer is in 8 bits. The target frequency of the processor is 10mHz
### Core architecture ### Core architecture
![Computer diagram.](/Documents/Computer%20diagram.svg) ![Computer diagram.](/Documents/Computer%20diagram.svg)
<sub>Made with [Drawio](https://www.drawio.com/).</sub> <sub>Made with [Drawio](https://www.drawio.com/).</sub>
#### ALU functions ### Registers and memory map
###### Logic Functions
| Func | Description |
| :----: | :------------- |
| !A | Not A. |
| !B | Not B. |
| A+B | A or B. |
| AB | A and B. |
| A^B | A xor B. |
| !(A+B) | Not (A or B). |
| !(AB) | Not (A and B). |
| !(A^B) | Not (A xor B). |
###### Arithmetic Functions
| Func | Description |
| :----: | :---------- :
| A+1 |
| A-1 |
| A+B |
| A-B |
#### Registers
| Name | Long Name | Description | | Name | Long Name | Description |
| :--: | :---------------------- | :--------------------------- | | :--: | :---------------------- | :--------------------------- |
| IR | Instruction Register | Running instruction storage. | | IR | Instruction Register | Running instruction storage. |
| Acc | Accumulator Register | ALU output register. | | A | A Register | ALU first input register. |
| TMP1 | Temp 1 Register | ALU first input register. | | B | B Register | ALU second input register. |
| TMP2 | Temp 2 Register | ALU second input register. | | PSW | Program Status Word | Status flags. |
| PSW | Program Status Word | Status flags. | | MAR | Memory Address Register | RAM heap access address. |
| MAR | Memory Address Register | RAM heap access address. |
| SP | Stack pointer | RAM stack access pointer. | | SP | Stack pointer | RAM stack access pointer. |
###### PSW Structure ###### PSW Structure
@ -101,12 +74,6 @@ The computer is in 8 bits. The target frequency of the processor is 10mHz.
| 6 | | | | | 6 | | | |
| 7 | | | | | 7 | | | |
#### Memory map
| Address | Mapping |
| :-----: | :------ |
| 0x00 |
### The instruction set ### The instruction set
Every instruction is 1 to 3 bytes long. Every instruction is 1 to 3 bytes long.