2 Commits

Author	SHA1	Message	Date
Ulysse Cura	b6b3fbebdd	Simluation for RAM and RAM related registers.	2026-07-06 18:57:51 +02:00
Ulysse Cura	b1a22d425e	Starting architecture, schematic and simulation.	2026-07-06 01:26:41 +02:00