79 lines
3.0 KiB
Markdown
79 lines
3.0 KiB
Markdown
# Neoarcheon computer
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<sub>*Neoarcheon means "The new dawn of ancient times".
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It comes from "[Neo](https://en.wiktionary.org/wiki/neo-)", a prefix for "New", and "[Eoarchean](https://en.wikipedia.org/wiki/Eoarchean)", the era in which life began.*</sub>
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----------
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## Summary
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1. [Aims and challenges](#aims-and-challenges)
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2. [Design](#design)
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1. [Core architecture](#core-architecture)
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2. [Registers and memory map](#registers-and-memory-map)
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3. [The instruction set](#the-instruction-set)
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## Aims and challenges
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Make a turing complete computer from scratch.
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At first every part of the computer will be the "industrial" version :
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- The CPU from logic gates.
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- The RAM a [SRAM](https://en.wikipedia.org/wiki/Static_random-access_memory) chip (*[UM61256BK-20](/Documents/Datasheets/UM61256.pdf) from 1993*)
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- The ROM another chip (*[D27C010](/Documents/Datasheets/D27C010-200V10.pdf) from 1986 !*)
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Then the aim is to replace them with made from scratch versions.
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For the moment only the RAM is meant to be replaced with homemade [magnetic core RAM](https://en.wikipedia.org/wiki/Magnetic-core_memory).
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**NOT ANY SORTS OF AI WILL BE USED IN THIS PROJECT.**
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*Why ?*
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People in the 70s got someone on the moon with their brain, and made him come back.
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AI is useful for medicine, protein research or other deep research subjects.
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I do not need a LLM to understand and make a computer.
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## Design
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The design is inspired of great people hard work :
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- [Ben Eater's 8 bits breadboard computer](https://eater.net/8bit)
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- [Mattbatwings's Minecraft computer tutorial](https://youtu.be/hAZEXqWLTmY?si=qgic0b28PMeOPs_l)
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The core architecture is inspired of the legendary [Intel's MCS-51](/Documents/Datasheets/8051.PDF) [microcontroller series](https://en.wikipedia.org/wiki/Intel_MCS-51).
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The computer is in 8 bits. The target frequency of the processor is 10mHz
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### Core architecture
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<sub>Made with [Drawio](https://www.drawio.com/).</sub>
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### Registers and memory map
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| Name | Long Name | Description |
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| :--: | :---------------------- | :--------------------------- |
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| IR | Instruction Register | Running instruction storage. |
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| A | A Register | ALU first input register. |
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| B | B Register | ALU second input register. |
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| PSW | Program Status Word | Status flags. |
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| MAR | Memory Address Register | RAM heap access address. |
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| SP | Stack pointer | RAM stack access pointer. |
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###### PSW Structure
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| Bit | Name | Description |
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| :-: | :--: | :---------- |
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| 0 |
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### The instruction set
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Every instruction is 1 to 3 bytes long.
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First is the opcode, and the optionnal 2 bytes are the operands.
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Operands can be an data (1B), address (1B), or full address (2B).
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These are only real instructions. Pseudoinstruction will be defined later.
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| Mnemonic | Description | Pseudocode |
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| :-------: | :------------ | :------------ |
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