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Starting to add PSW Register.

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Ulysse Cura 2026-07-06 15:13:38 +02:00
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README.md
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@ -60,9 +60,16 @@ The CPU will have ports for inputs / outputs, not a north and south bridge.
| IR | Instruction Register | Running instruction storage. | | IR | Instruction Register | Running instruction storage. |
| A | A Register | ALU first input register. | | A | A Register | ALU first input register. |
| B | B Register | ALU second input register. | | B | B Register | ALU second input register. |
| PSW | Program Status Word | Status flags. |
| MAR | Memory Address Register | RAM heap access address. | | MAR | Memory Address Register | RAM heap access address. |
| SP | Stack pointer | RAM stack access pointer. | | SP | Stack pointer | RAM stack access pointer. |
###### PSW Structure
| Bit | Name | Description |
| :-: | :--: | :---------- |
| 0 |
### The instruction set. ### The instruction set.
Every instruction is 1 to 3 bytes long. Every instruction is 1 to 3 bytes long.