 Ulysse Cura
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c2446b9b2d
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Updated diagram.
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2026-07-10 11:42:02 +02:00 |
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Ulysse Cura
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49a87423b2
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Added license.
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2026-07-07 01:17:31 +02:00 |
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Ulysse Cura
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dddb1629a6
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Original diagram.
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2026-07-07 01:17:19 +02:00 |
Ulysse Cura
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88a38a8c34
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Adding Logo.
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2026-07-07 01:13:45 +02:00 |
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Ulysse Cura
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2de5750a81
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Adding ALU in simulation.
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2026-07-07 01:10:52 +02:00 |
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Ulysse Cura
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dbcb0a6ffb
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Pseudoinstruction swaped with instructions.
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2026-07-07 01:10:37 +02:00 |
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Ulysse Cura
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afc6c17648
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PSW register structure.
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2026-07-07 01:10:15 +02:00 |
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Ulysse Cura
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f6643efaec
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Typo in french README.
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2026-07-06 19:23:11 +02:00 |
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Ulysse Cura
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2f6d31febc
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Updated computer digram.
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2026-07-06 18:58:06 +02:00 |
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Ulysse Cura
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b6b3fbebdd
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Simluation for RAM and RAM related registers.
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2026-07-06 18:57:51 +02:00 |
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Ulysse Cura
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00bd250808
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README fr.
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2026-07-06 16:39:21 +02:00 |
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Ulysse Cura
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a81bd74d9c
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Typos.
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2026-07-06 16:38:58 +02:00 |
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Ulysse Cura
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8182769e79
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Starting to add PSW Register.
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2026-07-06 15:13:38 +02:00 |
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Ulysse Cura
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0fb4cd8a0f
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Better diagram credits.
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2026-07-06 15:13:17 +02:00 |
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Ulysse Cura
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98c842bed4
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Refoctoring of README.
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2026-07-06 15:13:01 +02:00 |
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Ulysse Cura
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8a8da3ec39
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Give a name to the computer.
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2026-07-06 15:12:15 +02:00 |
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Ulysse Cura
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1f6ed34154
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Updated diagram.
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2026-07-06 15:11:56 +02:00 |
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Ulysse Cura
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3e3a3a5de3
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Removed .history folder.
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2026-07-06 01:27:50 +02:00 |
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Ulysse Cura
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b1a22d425e
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Starting architecture, schematic and simulation.
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2026-07-06 01:26:41 +02:00 |
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Ulysse Cura
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783a8ae58a
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AI warning.
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2026-07-05 16:13:16 +02:00 |
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Ulysse Cura
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85d6b4b221
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Documents, summary and starting instruction set.
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2026-07-05 16:03:14 +02:00 |
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Ulysse Cura
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617fcce334
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First commit
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2026-07-03 02:28:27 +02:00 |